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zephyr: fix secondary core power-up sequence with CONFIG_PM
When Zephyr PM subsystem is not used and SOF legacy runtime_pm framework is used instead, we need to keep runtime_pm separately up-to-date on the core power status, even if we use Zephyr interfaces to actually do the power up/down of a core. Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
1 parent 246ef6d commit 7ce8799

2 files changed

Lines changed: 5 additions & 3 deletions

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src/lib-zephyr/cpu.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -97,6 +97,9 @@ int cpu_enable_core(int id)
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atomic_set(&start_flag, 1);
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#ifndef CONFIG_PM
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w_core_enable_mask |= BIT(id);
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/* keep pm_runtime up-to-speed with core power status */
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pm_runtime_get(PM_RUNTIME_DSP, PWRD_BY_TPLG | id);
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#endif
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return 0;
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}

src/platform/intel/cavs/lib/pm_runtime.c

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Original file line numberDiff line numberDiff line change
@@ -428,13 +428,12 @@ static inline void cavs_pm_runtime_dis_dsp_pg(uint32_t index)
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lps_ctl |= SHIM_LPSCTL_FDSPRUN;
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shim_write(SHIM_LPSCTL, lps_ctl);
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} else {
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#ifdef __ZEPHYR__
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#ifndef __ZEPHYR__
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/*
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* In Zephyr secondary power-up needs to go via Zephyr
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* SMP kernel core, so we can't program PWRCTL directly here.
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*/
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cpu_enable_core(index);
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#else
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/* Secondary core power up */
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shim_write16(SHIM_PWRCTL, shim_read16(SHIM_PWRCTL) |
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SHIM_PWRCTL_TCPDSPPG(index) |

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