Skip to content

[xpu][test][dtypes] Finish XPU enablement of test_affine_quantized_float - #4637

Open
karol-brejna-i wants to merge 1 commit into
pytorch:mainfrom
karol-brejna-i:dev/kbrejna/affine-quantized-float-ut-enablement
Open

[xpu][test][dtypes] Finish XPU enablement of test_affine_quantized_float#4637
karol-brejna-i wants to merge 1 commit into
pytorch:mainfrom
karol-brejna-i:dev/kbrejna/affine-quantized-float-ut-enablement

Conversation

@karol-brejna-i

@karol-brejna-i karol-brejna-i commented Jul 29, 2026

Copy link
Copy Markdown

Summary

Two targeted fixes to complete XPU enablement of test/dtypes/test_affine_quantized_float.py:

  1. test_per_row_with_float32 — last CUDA-hardcoded test

Replaces the torch.cuda.is_available() skip and hardcoded "cuda" device with the device-agnostic pattern.

  1. Fix broken gate on test_dequantize_affine_float8 (line 144)

The previous gate was:

torch.cuda.is_available() == "cuda" and not is_sm_at_least_89()

torch.cuda.is_available() returns bool, not a string, so this comparison is always False. The sm89 requirement was never enforced on pre-sm89 CUDA hardware. This is a leftover from the earlier partial device-agnostic conversion (the sibling test test_choose_scale_float8_bounds already carries the correct torch.cuda.is_available() and not is_sm_at_least_89() form). Fixed to the correct form.

Validation

All checks performed on an XPU machine (torch 2.14.0.dev20260714+xpu):

  • Before/after run:**
    • Before (main): 28 passed, 1 skipped
    • After (this PR): 29 passed, 0 skipped
  • Static check — ruff check and ruff format --check both clean. Grep sweep for .cuda()/device="cuda"/hardcoded skip strings returns nothing. Remaining torch.cuda.is_available() occurrences are all properly paired with and not is_sm_at_least_89().

Most tests in this file are already device-agnostic. Two gaps remain:

1. test_per_row_with_float32 was still CUDA-only:
   - gate -> torch.accelerator.is_available()
   - is_sm_at_least_89() scoped behind torch.cuda.is_available(), so the
     sm89 requirement still applies to CUDA but does not exclude XPU
   - .to("cuda") -> .to(get_current_accelerator_device()), resolved in
     the test body
   The assertion under test is raised in _input_activation_quant_func_fp8
   after _fp8_mm_compat(), which only checks tensor rank and that both
   dims are multiples of 16 - no device or vendor probe - so a 64x64
   model raises it on any accelerator before any fp8 kernel runs.

2. Non-XPU fix: the gate on test_dequantize_affine_float8 compared a
   bool to a string (torch.cuda.is_available() == "cuda"), so it was
   always False and the sm89 requirement was never enforced on CUDA.
   No effect on sm89+ or XPU; pre-sm89 NVIDIA now correctly skips.

test_quantize_dequantize_fp8_inductor is left alone: it is CPU-only by
construction and making it accelerator-aware needs XPU inductor codegen
expectations, which is separate scope.

Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
@pytorch-bot

pytorch-bot Bot commented Jul 29, 2026

Copy link
Copy Markdown

🔗 Helpful Links

🧪 See artifacts and rendered test results at hud.pytorch.org/pr/pytorch/ao/4637

Note: Links to docs will display an error until the docs builds have been completed.

❌ You can merge normally! (5 Unrelated Failures), 1 Unclassified Failure

As of commit 72c043e with merge base 03ca489 (image):

UNCLASSIFIED FAILURE - DrCI could not classify the following job because the workflow did not run on the merge base. The failure may be pre-existing on trunk or introduced by this PR:

  • xpu-test / test (gh) (this job did not run on the merge base, so DrCI cannot tell whether the failure is pre-existing)
    torchao/test/prototype/test_int4_opaque_tensor.py::TestInt4OpaqueTensor::test_module_path_float32_use_hqq_True

BROKEN TRUNK - The following jobs failed but were present on the merge base:

👉 Rebase onto the `viable/strict` branch to avoid these failures

This comment was automatically generated by Dr. CI and updates every 15 minutes.

@meta-cla meta-cla Bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Jul 29, 2026
@karol-brejna-i
karol-brejna-i marked this pull request as draft July 29, 2026 07:58
@liangan1 liangan1 added ciflow/xpu label used to trigger xpu CI jobs xpu Intel XPU related features labels Jul 29, 2026
@karol-brejna-i

Copy link
Copy Markdown
Author

Need to wait until CI "global" fail will be over (see: #4625).

@karol-brejna-i karol-brejna-i changed the title [xpu][dtypes][test] Finish XPU enablement of test_affine_quantized_float [xpu][test][dtypes] Finish XPU enablement of test_affine_quantized_float Jul 29, 2026
@karol-brejna-i
karol-brejna-i marked this pull request as ready for review July 29, 2026 19:21
@jerryzh168

Copy link
Copy Markdown
Contributor

affine_quantized_float is deprecated now I think, cc @andrewor14 @vkuzo maybe migrate useful tests to test_float8_tensor and remove the file?

@karol-brejna-i

Copy link
Copy Markdown
Author

@pytorchbot label "module: not user facing"

@pytorch-bot pytorch-bot Bot added the module: not user facing Use this tag if you don't want this PR to show up in release notes label Jul 31, 2026
@pytorch-bot

pytorch-bot Bot commented Jul 31, 2026

Copy link
Copy Markdown

The ciflow label(s) ciflow/xpu will be added, but CI won't be triggered until the workflows are approved (scroll to the bottom of this page).

Please ping one of the reviewers if you do not have access to approve and run workflows.

@liangan1 liangan1 added ciflow/xpu label used to trigger xpu CI jobs xpu Intel XPU related features and removed ciflow/xpu label used to trigger xpu CI jobs xpu Intel XPU related features labels Jul 31, 2026
@pytorch-bot

pytorch-bot Bot commented Jul 31, 2026

Copy link
Copy Markdown

Workflows were awaiting approval. CI has now been triggered for the ciflow labels on this PR.

@liangan1 liangan1 added ciflow/xpu label used to trigger xpu CI jobs xpu Intel XPU related features and removed ciflow/xpu label used to trigger xpu CI jobs xpu Intel XPU related features labels Aug 3, 2026
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

ciflow/xpu label used to trigger xpu CI jobs CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. module: not user facing Use this tag if you don't want this PR to show up in release notes xpu Intel XPU related features

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants