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ASoC: SOF: Intel: hda-loader: clear the IPC ack bit after FW_PURGE done #1458

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Merged
plbossart merged 1 commit into from
Nov 11, 2019
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ASoC: SOF: Intel: hda-loader: clear the IPC ack bit after FW_PURGE done #1458

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6 changes: 6 additions & 0 deletions sound/soc/sof/intel/hda-loader.c
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Original file line number Diff line number Diff line change
Expand Up @@ -131,6 +131,12 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
goto err;
}

/* set DONE bit to clear the reply IPC message */
snd_sof_dsp_update_bits_forced(sdev, HDA_DSP_BAR,
chip->ipc_ack,
chip->ipc_ack_mask,
chip->ipc_ack_mask);

@plbossart plbossart Nov 8, 2019

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Maybe the sequence is correct, but the commit message and comment could be improved:

  1. what does 'clear the reply IPC message' mean? You only enable IPC interrupts in step 6.
  2. There is nothing in this code which refers to a PURGE_IPC, so some background information is missing. There is a purge request

Looks like there are two forms of IPC and two types of DONE bits...

@keyonjie keyonjie Nov 8, 2019

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Maybe the sequence is correct, but the commit message and comment could be improved:

  1. what does 'clear the reply IPC message' mean? You only enable IPC interrupts in step 6.

There is no IPC interrupt at this point, but there do be IPC message here, those IPC registers are being set, without triggering an IPC IRQ. :)

  1. There is nothing in this code which refers to a PURGE_IPC, so some background information is missing. There is a purge request

It is in some lines above, the step /* step 2: purge FW request */

Looks like there are two forms of IPC and two types of DONE bits...

@xiulipan xiulipan Nov 11, 2019 •
edited by keyonjie
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@keyonjie The point here is to clear the DONE bit from /* step 4: wait for IPC DONE bit from ROM */ right?
If we do not clear it before we enable IPC IRQ, we will that that error message later.

Exactly.

/* step 5: power down corex */
ret = hda_dsp_core_power_down(sdev,
chip->cores_mask & ~(HDA_DSP_CORE_MASK(0)));
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