A DW UART driver for Sue Creek

Kconfig

@@ -58,4 +58,22 @@ config BUILD_VM_ROM
 	help
 	  Select if you want to build VM ROM
 
+choice
+	prompt "Tracing mechanism"
+	default TRACE_DMA
+
+config TRACE_DMA
+	bool "Use DMA to host RAM for tracing"
+	depends on !SUECREEK
+	help
+	  This uses a DMA channel for tracing
+
+config TRACE_UART
+	bool "Use a UART for tracing"
+	depends on UART
+	help
+	  Select this to use a UART for tracing
+
+endchoice
+
 endmenu

src/arch/xtensa/boot_loader.c

@@ -32,6 +32,7 @@
 #include <arch/wait.h>
 #include <sof/trace.h>
 #include <sof/io.h>
+#include <sof/uart.h>
 #include <uapi/user/manifest.h>
 #include <platform/platform.h>
 #include <platform/memory.h>
@@ -276,11 +277,25 @@ static int32_t lp_sram_init(void)
 }
 #endif
 
+#if defined(CONFIG_TRACE_UART)
+
+struct uart *trace_uart;
+
+static const struct uart_platform_data trace_uart_pdata = {
+	.port = PLATFORM_TRACE_UART_BASE,
+	.baud = PLATFORM_TRACE_UART_BAUD,
+};
+#endif
+
 /* boot master core */
 void boot_master_core(void)
 {
 	int32_t result;
 
+#if defined(CONFIG_TRACE_UART)
+	trace_use_uart(&trace_uart_pdata);
+#endif
+
 	/* TODO: platform trace should write to HW IPC regs on CNL */
 	platform_trace_point(TRACE_BOOT_LDR_ENTRY);
 

src/drivers/Kconfig

@@ -96,6 +96,17 @@ endmenu # "Decimation factors"
 
 endif # CAVS_DMIC
 
+config DW_UART
+	bool "DW UART driver"
+	default n
+	select UART
+	help
+	  Enable the DesignWare UART driver
+
+config UART
+	bool
+	default n
+
 endmenu # "Drivers"
 
 config CAVS_VERSION_1_5

src/drivers/dw/CMakeLists.txt

@@ -3,3 +3,8 @@ add_local_sources(sof dma.c)
 if(CONFIG_SUECREEK)
 	add_local_sources(sof gpio.c ssi-spi.c)
 endif()
+
+if(CONFIG_DW_UART)
+	add_local_sources(sof uart.c uart-write-word.c)
+	add_local_sources(bootloader uart-ll.c uart-write-word.c)
+endif()

src/drivers/dw/uart-ll.c

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2017-2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of the Intel Corporation nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <string.h>
+
+#include <sof/cpu.h>
+#include <sof/io.h>
+#include <sof/sof.h>
+#include <sof/string.h>
+#include <sof/uart.h>
+#include <sof/wait.h>
+
+#include <platform/platform.h>
+
+#include "uart-priv.h"
+
+static void dw_uart_write_word(struct uart *uart, uint32_t word)
+{
+	struct dw_uart_device *dev = container_of(uart, struct dw_uart_device,
+						  common);
+
+	dw_uart_write_word_internal(dev, word);
+}
+
+#define uart_write_reg dw_uart_write_common
+#define uart_read_reg dw_uart_read_common
+
+static struct uart_ops dw_uart_ll_ops = {
+	.write_word = dw_uart_write_word,
+};
+
+static struct dw_uart_device trace_uart_dev = {
+	.common.ops = &dw_uart_ll_ops,
+	.retry = PLATFORM_UART_RETRY,
+};
+
+struct uart *dw_uart_init(const struct uart_platform_data *pdata)
+{
+	struct dw_uart_device *dev = &trace_uart_dev;
+	uint32_t divisor, tmp;
+
+	dev->common.pdata = pdata;
+
+	if (pdata->baud != 0) {
+		divisor = (PLATFORM_UART_CLK_FREQ / pdata->baud) >> 4;
+
+		/* configure the baudrate */
+		tmp = uart_read_reg(dev, SUE_UART_REG_LCR);
+		uart_write_reg(dev, SUE_UART_REG_LCR, LCR_DLAB_BIT);
+		uart_write_reg(dev, SUE_UART_REG_BRDL,
+			       (uint8_t)(divisor & 0xFF));
+		uart_write_reg(dev, SUE_UART_REG_BRDH,
+			       (uint8_t)((divisor >> 8) & 0xFF));
+
+		/* restore to access baudrate divisor registers */
+		uart_write_reg(dev, SUE_UART_REG_LCR, tmp);
+	}
+
+	/* 8-bit data, 1 stop-bit, no parity, clear DLAB */
+	uart_write_reg(dev, SUE_UART_REG_LCR,
+		LCR_DLS(3) | LCR_STOP(0) | LCR_PEN(0));
+
+	/* FIFO enalbe, mode0, Tx/Rx FIFO reset */
+	uart_write_reg(dev, SUE_UART_REG_FCR, FCR_FIFO_RX_8 | FCR_FIFO_TX_0 |
+		FCR_FIFOE(1) | FCR_MODE(0) | FCR_RCVR_RST | FCR_XMIT_RST);
+
+	/* reset port */
+	uart_write_reg(dev, SUE_UART_REG_RBR, 0);
+
+	/* disable all interrupts */
+	uart_write_reg(dev, SUE_UART_REG_IER, 0);
+
+	/* clear possibly pending interrupts */
+	tmp = uart_read_reg(dev, SUE_UART_REG_LSR);
+	tmp = uart_read_reg(dev, SUE_UART_REG_IIR);
+
+	return &dev->common;
+}

src/drivers/dw/uart-priv.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2017-2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of the Intel Corporation nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __INCLUDE_DW_UART_PRIV_H__
+#define __INCLUDE_DW_UART_PRIV_H__
+
+#include <sof/uart.h>
+
+/* uart register list */
+#define SUE_UART_REG_THR	0
+#define SUE_UART_REG_RBR	0
+#define SUE_UART_REG_BRDL	0
+#define SUE_UART_REG_BRDH	4
+#define SUE_UART_REG_IER	4
+#define SUE_UART_REG_FCR	8
+#define SUE_UART_REG_IIR	8
+#define SUE_UART_REG_LCR	0xC
+#define SUE_UART_REG_LSR	0x14
+#define SUE_UART_REG_USR	0x7C  /* UART Status reg. */
+#define SUE_UART_REG_TFL	0x80  /* Transmit FIFO Level reg. */
+#define SUE_UART_REG_CPR	0xF4  /* Component Parameter reg. */
+
+#define FCR_FIFO_RX_1		0x00 /* 1 byte in RCVR FIFO */
+#define FCR_FIFO_RX_4		0x40 /* RCVR FIFO 1/4 full  */
+#define FCR_FIFO_RX_8		0x80 /* RCVR FIFO 1/2 full */
+#define FCR_FIFO_RX_14		0xC0 /* RCVR FIFO 2 bytes below full */
+
+/* TX FIFO interrupt levels: trigger interrupt with this many bytes in FIFO */
+#define FCR_FIFO_TX_0		0x00 /* TX FIFO empty */
+#define FCR_FIFO_TX_2		0x10 /* 2 bytes in TX FIFO  */
+#define FCR_FIFO_TX_4		0x20 /* TX FIFO 1/4 full */
+#define FCR_FIFO_TX_8		0x30 /* TX FIFO 1/2 full */
+
+#define dw_uart_read_common(dev, reg)\
+	io_reg_read((dev)->common.pdata->port + reg)
+#define dw_uart_write_common(dev, reg, value)\
+	io_reg_write((dev)->common.pdata->port + reg, value)
+
+/* ier register */
+#define IER_PTIME		0x80
+#define IER_ETBEI		0x2
+
+/* iir register */
+#define IIR_THR_EMPTY		2 /* THR empty or TX FIFO below threshold */
+#define IIR_RX_AVAILABLE	4
+#define IIR_RX_STATUS		6 /* overrun, parity, framing, break */
+
+/* lcr register */
+/*
+ *	0x0 -- 5bits
+ *	0x1 -- 6bits
+ *	0x2 -- 7bits
+ *	0x3 -- 8bits
+ */
+#define LCR_DLS(x)	(x << 0)
+
+/* 0-1stop, 1-1.5stop */
+#define LCR_STOP(x)	(x << 2)
+
+/* 0-parity disabled, 1-parity enabled */
+#define LCR_PEN(x)	(x << 3)
+
+#define LCR_DLAB_BIT	0x80
+
+/* fcr register */
+/* 0-fifo disabled; 1-enabled */
+#define FCR_FIFOE(x)	(x << 0)
+/* 0-mode0, 1-mode1 */
+#define FCR_MODE(x)	(x << 3)
+#define FCR_RCVR_RST	0x2
+#define FCR_XMIT_RST	0x4
+
+/* lsr register */
+#define LSR_TEMT	0x40	/* transmitter empty */
+
+/* usr register */
+#define USR_TFNF	0x2	/* transmitter FIFO not full */
+
+struct dw_uart_device {
+	struct uart common;
+	uint32_t retry;
+};
+
+void dw_uart_write_word_internal(struct dw_uart_device *dev, uint32_t word);
+
+#endif

src/drivers/dw/uart-write-word.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2017-2018, Intel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *   * Neither the name of the Intel Corporation nor the
+ *     names of its contributors may be used to endorse or promote products
+ *     derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+#include <sof/io.h>
+#include <sof/sof.h>
+
+#include "uart-priv.h"
+
+#define uart_write_reg dw_uart_write_common
+#define uart_read_reg dw_uart_read_common
+
+void dw_uart_write_word_internal(struct dw_uart_device *dev, uint32_t word)
+{
+	uint8_t bytes[8];
+	uint32_t outchar;
+	int i, j;
+	uint32_t retry;
+
+	/* store 8 nibbles of a 32-bit word in an array */
+	for (i = 28, j = 0; j < ARRAY_SIZE(bytes); i -= 4, j++)
+		bytes[j] = (word >> i) & 0xF;
+
+	for (i = 0; i < ARRAY_SIZE(bytes) + 1; i++) {
+		if (i < ARRAY_SIZE(bytes))
+			outchar = bytes[i] > 9 ?
+				bytes[i] - 10 + 'A' : bytes[i] + '0';
+		else
+			/* add '\n' to jump to the new line after each output */
+			outchar = '\n';
+
+		/* wait for transmitter to become ready to accept a character */
+		retry = dev->retry;
+		while ((uart_read_reg(dev, SUE_UART_REG_LSR) & LSR_TEMT) == 0)
+			if (retry-- == 0)	/* don't wait too long time */
+				break;
+
+		/* write to output reg */
+		uart_write_reg(dev, SUE_UART_REG_THR, outchar);
+	}
+}