Hand-written SystemVerilog SIMD core (Fall 2025) followed by an Allo DSL/HLS redesign adding INT8 GEMM, ReLU, and fusion kernels (Spring 2026), targeting the Nexys A7.
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Updated
May 1, 2026 - Python
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vector-processor
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functional and timing simulator for VMIPS-like vector architecture
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Updated
May 3, 2026 - Python
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